`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:19:27 05/04/2013
// Design Name:   Adder
// Module Name:   T:/Lab3/tb_adder.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Adder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_adder;

	// Inputs
	reg [M - 1:0] a_in;
	reg [M - 1:0] b_in;
	// Outputs
	wire [(2 * M) - 1:0] d_out;

	// Instantiate the Unit Under Test (UUT)
	Adder #(.N(4)) uut (
		.a_in(a_in), 
		.b_in(b_in), 
		.d_out(d_out)
	);
	
	reg [M - 1 : 0] i;
	reg [M - 1 : 0] j;
	
	parameter M = 4;

	initial begin
		// Initialize Inputs
		a_in = 0;
		b_in = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		forever #5 clk <= ~clk;
	end
	
	initial begin
		#100;
		for (i = 0; i < 15; i = i + 1) begin
			for (j = 0; j < 15; j = j + 1) begin
				#10 b_in <= b_in + 1'b1;
			end
			#10 a_in <= a_in + 1'b1;
		end
	end
      
endmodule

